Dynamic sensing is commonly used to sense small bit-line differentials in certain types of memory systems. For example, synchronous random access memories (SRAMs) commonly use dynamic sensing. Dynamic sensing is typically implemented with dynamic amplifiers that must be precharged before a next sensing event. A reset signal, therefore, is needed to precharge the dynamic amplifiers to prepare for subsequent sensing events. A common method used to generate the reset signal is to return all of the addresses to zero, otherwise referred to as a return to zero (RTZ) scheme. The reset signal is used to reset all of the predecoders and dynamic sense amplifiers. In a typical RTZ scheme, each address buffer asserts two signals, the true address signal and its binary complement, where all of the true and complement address signals are returned to zero to effectuate the reset.
One RTZ scheme is to use the falling edge of an external clock as the reset event. Reliance on an external clock, however, is problematic and forces designers using the memory chip to meet specific timing requirements for the input clock signal. If the external clock signal has a low duty cycle and thus a short "on" pulse, the falling edge may arrive too soon and before the bit lines of the memory array can be sensed. The memory device thus malfunctions if reset too soon. On the other hand, if the external clock signal has a relatively high duty cycle, the device resets relatively late, which thereby increases power usage needlessly.
Another RTZ scheme is the use of a self-timed pulse. The width of the self-timed pulse, however, varies due to temperature, power supply and process of variations. Thus, the address buffers may be reset too soon before the data is sensed if the self-timed pulse width is too small. Alternatively, if the pulse width is too wide, the minimum cycle time is needlessly increased. The voltage and temperature dependence of a self-timed pulse causes operational changes and affects the timing of the memory, depending upon ambient conditions. A self-timed pulse is also process-dependent, where an arbitrary timing value is selected. A chosen timing period that is too short results in a significant loss of yield in the manufacturing process. A chosen timing period that is too long results in a significant increase in cycle time and unnecessary consumption of power.
The situation is made worse when attempting to create a separate control signal for sensing the dynamic amplifier because there is no tracking mechanism between the reset of the addresses and the enabling of the dynamic amplifiers. A new RTZ scheme is desired that allows for maximum time for resetting and equalization while also reducing power and improving cycle time. It is also desired to provide a memory device that works in various temperatures, power supply levels and process variations, that is not dependent upon external clock specifications and that is not subject to external clock jitter.